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| note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channel s. for information about device errata, click here: www.maxim-ic.com/errata . 1 of 24 rev: 042106 general description the ds80c310 is a fast 80c31/80c32-compatible microcontroller. it features a redesigned processor core without wasted clock and memory cycles. as a result, it executes every 8051 instruction between 1.5x and 3x faster than the original architecture for the same crystal speed. typical applications have a speed improvement of 2.5x using the same code and the same crystal. the ds80c310 offers a 33mhz maximum crystal speed, resulting in apparent execution speeds of 82.5mhz (approximately 2.5x). the ds80c310 is pin compatible with the standard 80c32 and includes standard resources such as three timer/counters, 256 bytes of ram, and a serial port. it also provides dual data pointers (dptrs) to speed block data memory moves. it also can adjust the speed of movx data memory access between two and nine machine cycles for flexibility in selecting external memory and peripherals. the ds80c310 offers upward compatibility with the ds80c320. features 80c32 compatible 8051 pin and instruction set compatible full-duplex serial port three 16-bit timer/counters 256 bytes scratchpad ram multiplexed address/data bus addresses 64kb rom and 64kb ram high-speed architecture 4 clocks/machine cycle (8051 = 12) runs dc to 33mhz clock rates single-cycle instruction in 121ns dual data pointer optional variable length movx to access fast/slow ram /peripherals 10 total interrupt sources with 6 external internal power-on reset circuit upwardly compatible with the ds80c320 available in 40-pin plastic dip, 44-pin plcc, and 44-pin tqfp pin configurations n ote: designers must have two documents to fully use all the features of this device: this data sheet and the high-speed microcontroller user?s guide, available on our website at www.maxim- ic.com/microcontrollers . data sheets contai n pin descriptions, f eature overviews, and electrical specifications, whereas the user?s g uide contains detailed inform ation about device features and operation. top view ds80c310 high-speed microcontrolle r www.maxim-ic.com
ds80c310 2 of 24 ordering information part temp range max clock speed (mhz) pin-package ds80c310-mcg 0 c to +70 c 25 40 plastic dip ds80c310-mcg+ 0 c to +70 c 25 40 plastic dip ds80c310-qcg 0 c to +70 c 25 44 plcc ds80c310-qcg+ 0 c to +70 c 25 44 plcc ds80c310-qng -40 c to +85 c 25 44 plcc ds80c310-qng+ -40 c to +85 c 25 44 plcc ds80c310-ecg 0 c to +70 c 25 44 tqfp ds80c310-ecg+ 0 c to +70 c 25 44 tqfp + denotes a lead-free/rohs-compliant device. figure 1. block diagram ds80c310 ds80c310 3 of 24 pin description pin pdip plcc tqfp name function port 1 (i/o). port 1 functions as both an 8-bit bidirectional i/o port and an alternate functional interface for timer 2 i/o and new external interrupts. the reset condition of port 1 is with all bits at logic 1. in this state, a weak pullup holds the port high. this condition also serves as an input mode, since any external circuit that writes to the port overcomes the weak pullup. when software writes a 0 to any port pin, the ds80c310 activates a strong pulldown that remains on until either a 1 is written or a reset occurs. writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup. once the momentary strong driver turns off, the port once again becomes the output high (and input) state. the alternate modes of port 1 are outlined as follows: pin pdip plcc tqfp port alternate function 1 2 40 p1.0 t2 external i/o for timer/counter 2 2 3 41 p1.1 t2ex timer/counter 2 capture/reload trigger 3 4 42 p1.2 ? ds80c320 has a serial port rxd 4 5 43 p1.3 ? ds80c320 has a serial port txd 5 6 44 p1.4 int2 external interrupt 2 (positive edge detect) 6 7 1 p1.5 int3 external interrupt 3 (negative edge detect) 7 8 2 p1.6 int4 external interrupt 4 (positive edge detect) 1?8 2?9 40?44, 1, 2, 3 p1.0?p1.7 8 9 3 p1.7 int5 external interrupt 5 (negative edge detect) 9 10 4 rst reset (input). the rst input pin contains a schmitt voltage input to recognize external active-high reset inputs. the pin also employs an internal pulldown resistor to allow for a combination of wired-or external reset sources. ds80c310 4 of 24 pin pdip plcc tqfp name function port 3 (i/o). port 3 functions as both an 8-bit bidirectional i/o port and an alternate functional interface for external interrupts, serial port 0, timer 0 and 1 inputs, rd and wr strobes. the reset condition of port 3 is with all bits at logic 1. in this state, a weak pullup holds the port high. this condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pullup. when software writes a 0 to any port pin, the ds80c310 will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. writing a 1 after the port has been at 0 will cause a strong transiti on driver to turn on, followed by a weaker sustaining pullup. once th e momentary strong driver turns off, the port once again becomes both the output high and input state. the alternate modes of port 3 are as follows: pin pdip plcc tqfp port alternate function 10 11 5 p3.0 rxd0 serial port 0 input 11 13 7 p3.1 txd0 serial port 0 output 12 14 8 p3.2 int0 external interrupt 0 13 15 9 p3.3 int1 external interrupt 1 14 16 10 p3.4 t0 timer 0 external input 15 17 11 p3.5 t1 timer 1 external input 16 18 12 p3.6 wr external data memory write strobe 10?17 11, 13?19 5, 7?13 p3.0?p3.7 17 19 13 p3.7 rd external data memory read strobe 18, 19 20, 21 14, 15 xtal2, xtal1 crystal oscillator pins. xtal1 and xtal2 provide support for parallel resonant, at-cut crystals. xtal1 also acts as an input in the event that an external clock s ource is used in place of a crystal. xtal2 serves as the output of the crystal amplifier. 20 1, 22, 23 16, 17, 39 gnd digital circuit ground 21 24 18 a8 (p2.0) 22 25 19 a9 (p2.1) 23 26 20 a10 (p2.2) 24 27 21 a11 (p2.3) 25 28 22 a12 (p2.4) 26 29 23 a13 (p2.5) 27 30 24 a14 (p2.6) 28 31 25 a15 (p2.7) address outputs (port 2) (output). port 2 serves as the msb for external addressing. p2.7 is a15 and p2.0 is a8. the ds80c310 automatically places the msb of an address on p2 for external rom and ram access. although port 2 can be accessed like an ordinary i/o port, the value stored on the port 2 latch is never seen on the pins (due to memory access). therefore, writing to port 2 in software is only useful for the instructions movx a, @ ri or movx @ ri, a. these instructions use the port 2 inte rnal latch to supply the external address msb; the port 2 latch value is supplied as the address information. ds80c310 5 of 24 pin pdip plcc tqfp name function 29 32 26 psen active-low program store enable (output). this signal is commonly connected to external rom memory as a chip enable. psen is driven high when data memory (ram) is being accessed through the bus and during a reset condition. 30 33 27 ale address latch enable (output). th e output functions as clock to latch the external address lsb from the multiplexed address/data bus on port 0. this signal is commonly connected to the latch enable of an external 373 family transparent latch. ale is forced high when the ds80c310 is in a reset condition. 31 35 29 ea active-low external access (input). this pin must be connected to ground for proper operation. 32 36 30 ad7 (p0.7) 33 37 31 ad6 (p0.6) 34 38 32 ad5 (p0.5) 35 39 33 ad4 (p0.4) 36 40 34 ad3 (p0.3) 37 41 35 ad2 (p0.2) 38 42 36 ad1 (p0.1) 39 43 37 ad0 (p0.0) address/data bus 0?7 (port 0) (i/o). port 0 is the multiplexed address/data bus. during the time when ale is high, the lsb of a memory address is presented. when ale falls to logic 0, the port transitions to a bidirectional data bus. this bus is used to read external rom and read/write external ram memory or peripherals. port 0 has no true port latch and cannot be written directly by software. the reset condition of port 0 is high. 40 44 38 v cc +5v power supply ? 12, 34 6, 28 n.c. no connection (reserved). these pins should not be connected. they are reserved for use with future devices in this family. compatibility the ds80c310 is a fully static, cmos, 8051-compatible microcontroller designed for high performance. in most cases the ds80c310 can drop into an existing socket for the 80c31 or 80c32 to significantly improve the operation. in general, software writt en for existing 8051-based systems works without modification on the ds80c310. the exception is critic al timing because the high-speed microcontroller performs its instructions much fast er than the original for any give n crystal selection. the ds80c310 runs the standard 8051 family instruction set and is pin co mpatible with dip, plcc, or tqfp packages. the ds80c310 is a streamlined version of the ds80c320. it maintains upward comp atibility but has fewer peripherals. the ds80c310 provides three 16-bit timer/counters, a fu ll-duplex serial port, and 256 bytes of direct ram. i/o ports have the same operation as a standa rd 8051 product. timers default to a 12 clock-per- cycle operation to keep their timing compatible with original 8051 family systems. however, timers are individually programmable to run at the new 4 clocks per cycle if desired. the ds80c310 provides several new hardware func tions that are contro lled by special function registers (sfrs). table 1 summarizes the sfrs. performance overview the ds80c310 features a high-speed 8051-compatible core. higher speed comes not just from increasing the clock frequency but from a newer, more efficient design. this updated core does not have the dummy memory cy cles that exist in a st andard 8051. a conventional 8051 generates machine cycles using the clock fr equency divided by 12. in the ds80c310, the same ds80c310 6 of 24 machine cycle takes 4 clocks. thus the fastest instruc tion, 1 machine cycle, execute s three times faster for the same crystal frequency. note that these are identical instructions. the majority of instructions on the ds80c310 will see the full 3-to-1 speed improvement. some instructions will get betw een 1.5 and 2.4 to 1 improvement. all instructions ar e faster than th e original 8051. the numerical average of all op co des gives approximately a 2.5-to-1 speed improvement. improvement of individual programs depends on the actual instruc tions used. speed-sensitive applications would make the most use of instructions that are three times faster. however, th e sheer number of 3-to-1 improved op codes makes dramatic speed improvements likely fo r any code. these architecture improvements and 0.8 m cmos produce a peak instruction cycle in 160ns (6.25mips). the dual data pointer feature also allows the user to eliminate wasted inst ructions when moving blocks of memory. instruction set summary all instructions in the ds80c310 perf orm the same functions as their 8051 counterparts. their effect on bits, flags, and other status functio ns is identical. however, the timi ng of each instruction is different. this applies both in absolute and relative number of clocks. for absolute timing of real-time events, the timing of software loops can be calculated using a table in the high-speed microcontroller user?s guide . however, counter/timers default to run at the older 12 clocks per increment. in this way, timer-based events occur at the standard intervals with software executing at higher speed. timers optionally can run at 4 clocks pe r increment to take advant age of faster processor operation. the relative time of two instructions might be different in the new arch itecture than it was previously. for example, in the original architecture the ?movx a, @ dptr? instruction and the ?mov direct, direct? instruction used 2 machine cycles or 24 oscillator cycles. therefore, they required the same amount of time. in the ds80c310, the movx instruct ion takes as little as 2 machine cycles or 8 oscillator cycles but the ?mov direct, direct? uses 3 machine cycles or 12 oscillator cy cles. while both are faster than their original counterparts, they now have different execution times. this is because the ds80c310 usually uses 1 instruction cycle for each instruction byte. the user concerned with precise program timing should examine the timing of each instruction for familia rity with the changes. note that a machine cycle now requires just 4 clocks, and provid es one ale pulse per cycl e. many instructions require only 1 cycle, but some require 5. in the original architecture, all were 1 or 2 cycles except for mul and div. refer to the high-speed microcontroller user?s guide for details and indivi dual instruction timing. ds80c310 7 of 24 special function registers (sfrs) special function registers control most special features of the ds80c310. the high-speed microcontroller user?s guide contains descriptions of all the sfrs. functions that are not part of the standard 80c32 are in bold. table 1. special function registers register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address sp ? ? ? ? ? ? ? ? 81h dpl ? ? ? ? ? ? ? ? 82h dph ? ? ? ? ? ? ? ? 83h dpl1 ? ? ? ? ? ? ? ? 84h dph1 ? ? ? ? ? ? ? ? 85h dps 0 0 0 0 0 0 0 sel 86h pcon smod sm0d0 ? ? gf1 gf0 stop idle 87h tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 88h tmod gate c/ t m1 m0 gate c/ t m1 m0 89h tl0 ? ? ? ? ? ? ? ? 8ah tl1 ? ? ? ? ? ? ? ? 8bh th0 ? ? ? ? ? ? ? ? 8ch th1 ? ? ? ? ? ? ? ? 8dh ckcon ? ? t2m t1m t0m md2 md1 md0 8eh p1 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 90h exif ie5 ie4 ie3 ie2 ? ? ? ? 91h scon smo/fe sm1 sm2 ren tb8 rb8 ti ri 98h sbuf ? ? ? ? ? ? ? ? 99h p2 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 a0h ie ea ? et2 es0 et1 ex1 et0 ex0 a8h saddr0 ? ? ? ? ? ? ? ? a9h p3 p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 b0h ip ? ? pt2 pso pt1 px1 pt0 px0 b8h saden0 ? ? ? ? ? ? ? ? b9h status 0 hip lip 1 1 1 1 1 c5h t2con tf2 exf2 rclk tclk exen2 tr2 c/ t2 cp/ rl2 c8h t2mod ? ? ? ? ? ? t2oe dcen c9h rcap2l ? ? ? ? ? ? ? ? cah rcap2h ? ? ? ? ? ? ? ? cbh tl2 ? ? ? ? ? ? ? ? cch th2 ? ? ? ? ? ? ? ? cdh psw cy ac f0 rs1 rs0 ov fl p d0h wdcon ? por ? ? ? ? ? ? d8h acc ? ? ? ? ? ? ? ? e0h eie ? ? ? ? ex5 ex4 ex3 ex2 e8h b ? ? ? ? ? ? ? ? f0h eip ? ? ? ? px5 px4 px3 px2 f8h ds80c310 8 of 24 memory access the ds80c310 has 256 bytes of scratchpad ram, but contains no on-chip rom. off-chip memory is accessed using the multiplexed address/data bus on p0 and the msb address on p2. timing diagrams are provided in the absolute maximum ratings section. program memory (rom ) is accessed at a fixed rate determined by the crystal frequency and the actual inst ructions. as mentioned abov e, an instruction cycle requires 4 clocks. data memory (ram) is accessed acco rding to a variable speed movx instruction as described below. stretch memory cycle the ds80c310 allows the application software to adjust the speed of data memory access. the microcontroller can perform the movx in as few as 2 instruction cycles. howeve r, this value can be stretched as needed so that both fast memory and slow memory or peripherals can be accessed with no glue logic. even in high-speed sy stems, it may not be necessary or desirable to perform data memory access at full speed. in addition, there are a variety of memory-mapped peripherals such as lcd displays or uarts that are not fast. the stretch movx is controlled by the clock control register at sfr location 8eh as described below. this allows the user to select a stretch value between 0 and 7. a stretch of 0 results in a 2-machine-cycle movx. a stretch of 7 results in a movx of 9 mach ine cycles. software can dynamically change this value depending on the particular memory or peripheral. on reset, the stretch value defaults to 1, resul ting in a 3-cycle movx. th erefore, ram access is not performed at full speed. this is a convenience to exis ting designs that may not have fast ram in place. when maximum speed is desired, the software should select a stretch va lue of 0. when using very slow ram or peripherals, a larger stretch value can be selected. note th at this affects data memory only and the only way to slow program memory (r om) access is to use a slower crystal. using a stretch value between 1 and 7 causes the microc ontroller to stretch the read/write strobe and all related timing. this results in a wider read/write strobe allowing more time for memory/peripherals to respond. the timing of the variab le speed movx is shown in the absolute maximum ratings section. note that full speed access is not the reset default cas e. table 2 shows the resul ting strobe widths for each stretch value. the memory stretch is implemented using the clock cont rol special function register at sfr location 8eh. the stretch value is selected usi ng bits ckcon.2?ckcon.0. in the table, these bits are referred to as m2 through m0. the first stretc h (default) allows the use of common 120ns or 150ns rams without dramatically le ngthening the memory access. ds80c310 9 of 24 table 2. data memory cycle stretch values ckcon.2?ckcon.0 strobe width time (ns) m2 m1 m0 memory cycles rd or wr stroe width at 25mhz at 33mhz 0 0 0 2 2 80 60 0 0 1 3 (default) 4 160 121 0 1 0 4 8 320 242 0 1 1 5 12 480 364 1 0 0 6 16 640 485 1 0 1 7 20 800 606 1 1 0 8 24 960 727 1 1 1 9 28 1120 848 dual data pointer (dptr) data memory block moves can be accelerated us ing the ds80c310 dual data pointer (dptr). the standard 8032 dptr is a 16-bit value that is used to address off-chip data ram or peripherals. in the ds80c310, the standard data pointer is called dptr and is locat ed at sfr addresses 82h and 83h. these are the standard locations. no modi fication of standard code is needed to use dptr. the new dptr is located at sfr 84h and 85h and is called dptr1. the dptr select bit (dps) c hooses the active pointer and is located at the lsb of the sfr location 86h. no ot her bits in register 86h ha ve any effect and are set to 0. the user switches between data pointers by toggling the lsb of register 86h. the increment (inc) instruction is the fastest way to accomplish this. all dptr-related instructions use the currently selected dptr for any activity. therefore, only one instruction is required to switch from a source to a destination address. using the dptr saves code from needing to save source and destination addresses when doing a block move. once loaded, the software simply switc hes between dptr0 and 1. the relevant register locations are as follows. dpl 82h low byte original dptr dph 83h high byte original dptr dpl1 84h low byte new dptr dph1 85h high byte new dptr dps 86h dptr select (lsb) stop mode enhancements setting bit 1 of the power control register (pcon; 87h) invokes the stop mode. stop mode is the lowest power state because it turns o ff all internal clocking. the i cc of a standard stop mode is approximately 1 a (but is specified in the absolute maximum ratings section). the cpu exits stop mode from an external interrupt or a reset conditi on. internally generated interrupts are not useful since they require clocking activity. the ds80c310 allows a resume from stop using int2?i nt5, which are edge-triggered interrupts. an internal crystal counter ma nages the startup timing. a delay of 65, 536 clocks occurs to allow the crystal time to stabilize. software must al so insert a delay of 100 machine cy cles following the exit from stop mode. this ensures stabilization of internal timing prior to time-critical software tasks such as serial port operations or bus access to memory-mapped i/o devices. ds80c310 10 of 24 peripheral overview the ds80c310 provides the same peripheral functions as the standard 80c32. the device is compatible with the ds80c320, but it does no t offer all the peripherals. timer rate control there is one important difference between the ds 80c310 and 8051 regarding timers. the original 8051 used 12 clocks per cycle for timers and machine cy cles. the ds80c310 architecture normally uses 4 clocks per machine cycle. however, in the area of timers and serial ports, the ds80c310 defaults to 12 clocks per cycle on reset. this allo ws existing code with real-time de pendencies such as baud rates to operate properly. if an application needs higher speed timers or serial ba ud rates, the user can select individual timers to run at the 4-clock rate. the clock cont rol register (ckcon; 8eh) determines these timer speeds. when the relevant ckcon bit is logic 1, th e ds80c310 uses 4 clocks per cycle to generate timer speeds. when the bit is 0, the ds80c310 uses 12 clocks for timer speed s. the reset condition is 0. ckcon.5 selects the speed of timer 2. ckcon.4 selects timer 1 and ck con.3 selects timer 0. note that unless a user desires very fast timing, it is unnecessary to alter these bits. also note that the timer controls are independent. power-on reset the ds80c310 holds itself in reset during a power-up until 65,536 clock cycles ha ve elapsed. the power- on reset used by the ds80c310 differs somewhat from other members of the high-speed microcontroller family. the crystal oscillator can start anywhere between 1.0v and 4.5v, but is not specified. this eliminates the need for an rc reset circuit. for voltage-specific precisio n-brownout detection, an external component is needed. when the device goes through a power-on reset, the por flag is set in the wdcon (d8h) register at bit 6. interrupts the ds80c310 provides 10 interrupt sour ces with two priority levels. software can assign high or low priority to all sources. a ll interrupts that are new to the 8051 have a lower natural pr iority than the originals. table 3. interrupt sources and priorities name description vector natural priority int0 external interrupt 0 03h 1 tf0 timer 0 0bh 2 int1 external interrupt 1 13h 3 tf1 timer 1 1bh 4 scon t1 or r1 from the serial port 23h 5 tf2 timer 2 2bh 6 int2 external interrupt 2 43h 7 int3 external interrupt 3 4bh 8 int4 external interrupt 4 53h 9 int5 external interrupt 5 5bh 10 ds80c310 11 of 24 absolute maxi mum ratings voltage range on any pin relative to ground??????????????...-0.3v to (v cc + 0.5v) voltage range on v cc relative to ground???????????????????.-0.3v to +6.0v operating temper ature range????????????????????????-40 c to +85 c storage temperat ure range????????????????????????.-55 c to +125 c soldering temperatur e????????????????.see ipc/jedec j-std-020 specification this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in t he operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. dc electrical characteristics (v cc = 4.5v to 5.5v, t a = -40 c to +85 c.) (note 1) parameter symbol min typ max units notes supply voltage v cc 4.0 5.0 5.5 v 2 supply current active mode at 33mhz i cc 30 ma 3 supply current idle mode at 33mhz i idle 15 ma 4 supply current stop mode i stop 1 a 5 input low level v il -0.3 +0.8 v 2 input high level (except xtal1 and rst) v ih 2.0 v cc + 0.3 v 2 input high level xtal1 and rst v ih2 3.5 v cc + 0.3 v 2 output low voltage ports 1, 3 at i ol = 1.6ma v ol1 0.15 0.45 v 2 output low voltage port 0, 2, ale, psen at i ol = 3.2ma v ol2 0.15 0.45 v 2, 6 output high voltage port 1, 3, ale, psen at i oh = -50 a v oh1 2.4 v 2, 7 output high voltage ports 1, 3 at i oh = -1.5ma v oh2 2.4 v 2, 8 output high voltage port 0, 2, ale, psen at i oh = -8ma v oh3 2.4 v 2, 6 input low current ports 1, 3 at 0.45v i il -55 a 9 transition current from 1 to 0 ports 1, 3 at 2v i tl -650 a 10 input leakage port 0, bus mode i l -300 +300 a 11 rst pulldown resistance r rst 50 170 k ? note 1: all parameters apply to both commercial and industrial temper ature operation unless otherwise noted. specifications to -40 c are guaranteed by design and not product tested. note 2: all voltages are referenced to ground. note 3: active current is measured with a 25mhz clock source driving xtal1, v cc = rst = 5.5v, all ot her pins disconnected. note 4: idle mode current is measured with a 25mhz clock source driving xtal1, v cc = 5.5v, rst at ground, all other pins disconnected. note 5: stop mode current measured with xtal1 and rst grounded, v cc =5.5v, all other pins disconnected. ds80c310 12 of 24 note 6: when addressing external memory. this specification applies to the first clock cycle following the transition. on subsequent cycles following 1 to 0 transitions, the typical current si nk capability of port 0 an d port 2 is approximately 150 a, and the minimum current sink capability of ale and psen is approximately 400 a. on subsequent cycles following 0 to 1 transitions, the typical current drive capability of port 0 and port 2 is approximately 110 a. note 7: rst = v cc . this condition mimics operation of pins in i/o mode. note 8: during a 0 to 1 transition, a one-shot drives the ports hard for two clock cycles. this measurem ent reflects port in transition mode. note 9: current required from external circuit to hold a logic-low leve l on an i/o pin while the corresponding port latch bit is set to 1. this is only the current required to hold the low level; tran sitions from 1 to 0 on an i/o pin must also overcome the transitio n current. note 10: ports 1 and 3 source transition current when being pulled down ex ternally. the current reaches its maximum at approximately 2v. note 11: 0.45 < v in ds80c310 14 of 24 movx characteristics variable clock parameter symbol min max units stretch (note 1) 1.5t clcl -5 t mcs =0 data access ale pulse width t lhll2 2t clcl -5 ns t mcs >0 0.5t clcl -5 t mcs =0 port 0 address valid to ale low t avll2 t clcl -5 ns t mcs >0 0.5t clcl -15 t mcs =0 address hold after ale low for movx write t llax2 t clcl -7 ns t mcs >0 2t clcl -5 t mcs =0 rd pulse width t rlrh t mcs -10 ns t mcs >0 2t clcl -5 t mcs =0 wr pulse width t wlwh t mcs -10 ns t mcs >0 2t clcl -20 t mcs =0 rd low to valid data in t rldv t mcs -20 ns t mcs >0 data hold after read t rhdx 0 ns t clcl -5 t mcs =0 data float after read t rhdz 2t clcl -5 ns t mcs >0 2.5t clcl -28 t mcs =0 ale low to valid data in t lldv t clcl +t mcs -40 ns t mcs >0 3t clcl -22 t mcs =0 port 0 address to valid data in t avdv1 2.0t clcl+ t mcs - 25 ns t mcs >0 3.5t clcl -35 t mcs =0 port 2 address to valid data in t avdv2 2.5t clcl+ t mcs - 35 ns t mcs >0 0.5t clcl -14 0.5t clcl +5 t mcs =0 ale low to rd or wr low t llwl t clcl -8 t clcl +5 ns t mcs >0 t clcl -9 t mcs =0 port 0 address to rd or wr low t avwl1 2t clcl -8 ns t mcs >0 1.5t clcl -10 t mcs =0 port 2 address to rd or wr low t avwl2 2.5t clcl -10 ns t mcs >0 data valid to wr transition t qvwx -14 ns t clcl -11 t mcs =0 data hold after write t whqx 2t clcl -10 ns t mcs >0 rd low to address float t rlaz (note 2) ns 0 10 t mcs =0 rd or wr high to ale high t whlh t clcl -5 t clcl +9 ns t mcs >0 note 1: t mcs is a time period related to the stretch memory cycle selection. the following table shows the value of t mcs for each stretch selection. m2 m1 m0 movx cycles t mcs 0 0 0 2 machine cycles 0 0 0 1 3 machine cycles (default) 4 t clcl 0 1 0 4 machine cycles 8 t clcl 0 1 1 5 machine cycles 12 t clcl 1 0 0 6 machine cycles 16 t clcl 1 0 1 7 machine cycles 20 t clcl 1 1 0 8 machine cycles 24 t clcl 1 1 1 9 machine cycles 28 t clcl ds80c310 15 of 24 note 2: address is held in a weak latch until overdriven by external memory. external clock characteristics parameter symbol min typ max units clock high time t chcx 10 ns clock low time t clcx 10 ns clock rise time t clcl 5 ns clock fall time t chcl 5 ns serial port mode 0 timing characteristics parameter symbol conditions min typ max units sm2 = 0, 12 clocks per cycle 12t clcl serial port clock cycle time t xlxl sm2 = 1, 4 clocks per cycle 4t clcl ns sm2 = 0, 12 clocks per cycle 10t clcl output data setup to clock rising t qvxh sm2 = 1, 4 clocks per cycle 3t clcl ns sm2 = 0, 12 clocks per cycle 2t clcl output data hold from clock rising t xhqx sm2 = 1, 4 clocks per cycle t clcl ns sm2 = 0, 12 clocks per cycle t clcl input data hold after clock rising t xhdx sm2 = 1, 4 clocks per cycle t clcl ns sm2 = 0, 12 clocks per cycle 11t clcl clock rising edge to input data valid t xhdv sm2 = 1, 4 clocks per cycle 3t clcl ns definition of ac symbols in an effort to remain compatible with the original 8051 family, this device specifies the same parameters as such devices, using the same sym bols. for completeness, the following are description of the symbols. t time a address c clock d input data h logic level high l logic level low i instruction p psen q output data r rd signal v valid w wr signal x no longer a valid logic level z tri-state ds80c310 16 of 24 external program memory read cycle ds80c310 17 of 24 external data memory read cycle ds80c310 18 of 24 data memory write cycle data memory write with stretch = 1 ds80c310 19 of 24 data memory write with stretch = 2 external clock drive ds80c310 20 of 24 serial port mode 0 timing ds80c310 21 of 24 package information (the package drawing(s) in this data sheet may not reflect t he most current specifications . for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) ds80c310 22 of 24 package information (continued) (the package drawing(s) in this data sheet may not reflect t he most current specifications . for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) ds80c310 23 of 24 package information (continued) (the package drawing(s) in this data sheet may not reflect t he most current specifications . for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) ds80c310 24 of 24 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products ? printed usa the maxim logo is a registered trademark of maxim integrated produ cts, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. revision history revision description of change 090198 1) added note to clarify i il specification. 2) changed serial port mode 0 timing diagram label from t qvxl to t qvxh . 3) changed minimum oscillat or frequency to 1mhz when using external crystal. 4) corrected ?data memory write with stretc h? diagrams to show falling edge of ale coincident with rising edge of c3 clock. 012401 1) added errata disclaimer to page 1. 102405 1) device moved to qualified status. remove d ?preliminary? status from data sheet. 2) removed references to 33mhz versions of the device. 3) added note requiring 100 machine cycles de lay following stop mode exit. this edit transfers existing erratum from errata sheet into data sheet. 4) updated absolute maximum ratings table to match current format. 5) displayed electrical characteristics test conditions. 6) added notation that -40 c specifications are guaranteed by design but not tested. 7) clarified dc electrical characteristics not e that the specification only applies to the first clock cycle following the transition. 8) added lead-free part numbers to ordering information table. 9) added t avll2 specification. 10) updated ac timing characteristics with full characterization data. 042106 1) changed lead-free ordering information part numbers to correctly reflect that the ?+? comes after part numbers (e.g., ds80c310-mcg+). 2) added note 2 to the ac electrical char acteristics and movx characteristics tables (pages 13 and 14). ds80c310 part number table english ? ? ?Z ? ??? what's new products solutions design appnotes support buy company members notes: 1. see the ds80c310 quickview data sheet for further information on this product family or download the ds80c310 full data sheet (pdf, 756kb). 2. other options and links for pu rchasing parts are listed at: http://www.maxim-ic.com/sales . 3. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 4. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free ; # = rohs/lead-exempt. more: see full data sheet or part naming conventions . 5. * some packages have variations, listed on the drawing. "pkgcode/variation" te lls which variation the product uses. part number notes free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis ds80c310-fcg+ sample buy mqfp;44 pin;394 dwg: 56-g3001-001b (pdf) use pkgcode/vari ation: m44+10 * 0c to +70c rohs/lead-free: yes ds80c310-fcg sample buy mqfp;44 pin;394 dwg: 56-g3001-001b (pdf) use pkgcode/variation: m44-10 * 0c to +70c rohs/lead-free: no materials analysis ds80c310-mcg+ sample buy pdip;40 pin;600 dwg: 56-g5000-000a (pdf) use pkgcode/vari ation: p40+6 * 0c to +70c rohs/lead-free: yes materials analysis ds80c310-mcg 25mhz sample buy pdip;40 pin;600 dwg: 56-g5000-000a (pdf) use pkgcode/vari ation: p40-1 * 0c to +70c rohs/lead-free: no materials analysis ds80c310-qcg+ sample buy plcc;44 pin;652 dwg: 56-g4003-001b1 (pdf) use pkgcode/vari ation: q44+1 * 0c to +70c rohs/lead-free: yes materials analysis ds80c310-qcg 25mhz sample buy plcc;44 pin;652 dwg: 56-g4003-001b1 (pdf) use pkgcode/vari ation: q44-1 * 0c to +70c rohs/lead-free: no materials analysis pa g e 1 of 2 ds80c310 - part number table - maxim/dallas 30-jul-2007 mhtml:file://c:\te mp\maxm\ds80c310.mht didn't find what you need? ds80c310-qng sample buy plcc;44 pin;652 dwg: 56-g4003-001b1 (pdf) use pkgcode/vari ation: q44-1 * -40c to +85c rohs/lead-free: no materials analysis ds80c310-qng+ sample buy plcc;44 pin;652 dwg: 56-g4003-001b1 (pdf) use pkgcode/vari ation: q44+1 * -40c to +85c rohs/lead-free: yes materials analysis ds80c310-ecg 25mhz sample buy tqfp;44 pin;394 dwg: 56-g4012-001b (pdf) use pkgcode/variation: c44-2 * 0c to +70c rohs/lead-free: no materials analysis ds80c310-ecg+ sample buy tqfp;44 pin;394 dwg: 56-g4012-001b (pdf) use pkgcode/variation: c44+2 * 0c to +70c rohs/lead-free: yes materials analysis contact us: send us an email copyright ? 2007 by maxim integrated products, dallas semiconductor ? legal notices ? privacy policy pa g e 2 of 2 ds80c310 - part number table - maxim/dallas 30-jul-2007 mhtml:file://c:\te mp\maxm\ds80c310.mht |
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